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xtrinsic FXLC95000CL intelligent, motion-sensing platform the FXLC95000CL intelligent, motion-sensing platform is a breakthrough device with the integration of a 3-axis mems accelerometer and a 32-bit coldfire mcu that enables autonomous, high-precision sensing solutions with local computing and sensors management capability in an open, easy to use, architecture. the FXLC95000CL hardware is user-programmable to create an intelligent high-precision, flexible, motion-sensing platform. the user's firmware, together with the hardware device, can make system-level decisions required for sophisticated applications, such as gesture recognition, pedometer, and e-compass tilt compensation and calibration. the fxlc95000 platform can act as an intelligent sensing hub and a highly configurable decision engine. using the master i 2 c or spi module, the fxlc95000 platform can manage secondary sensors such as pressure sensors, magnetometers, and gyroscopes. the embedded microcontroller allows sensor integration, initialization, calibration, data compensation, and computation functions to be added to the platform, thereby off- loading those functions from the host processor. total system power consumption is significantly reduced because the application processor stays powered down for longer periods of time. the FXLC95000CL device is programmed and configured with codewarrior development studio for microcontroller (eclipse ide). this standard, integrated development environment (ide) enables customers to quickly implement custom embedded algorithms and features to exactly match their application needs. hardware features ? 3-axis low noise accelerometer ? 2 g, 4 g, 8 g configurable dynamic ranges available ? up to 16-bit resolution ? 32-bit mcu ? coldfire v1 cpu with mac hardware unit ? 128k flash, 16k ram, 16k rom ? 10-, 12-, 14-, and 16-bit, trimmed analog-to-digital converter (adc) data formats available ? master and slave, i 2 c and spi serial connectivity modules ? sleep and low power modes to enable local power FXLC95000CL 24-lead lga 3 mm by 5 mm by 1 mm case 2208-01 top view rgpio14 / scl1 rgpio15 / sda1 v ssio v ddio v dd bkgd-ms / rgpio9 resetb rgpio11 / mosi1 rgpio10 / sclk1 rgpio7 / an1+ / tpmch1 rgpio6 / an0- / tpmch0 rgpio5 / pdb_a / int_o v ss rgpio4 / int_i v ssa rgpio8 / pdb_b v dda rgpio13 / ssb1 rgpio12 / miso1 scl0 / rgpio0 / sclk v ss sda0 / rgpio1 / mosi rgpio2 / scl1 / miso rgpio3 / sda1 / ssb pin connections freescale semiconductor, inc. FXLC95000CL data sheet: technical data rev 1.2, 8/2013 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2012C2013 freescale semiconductor, inc. all rights reserved.
? wide operating voltage and temperature range ? 1.71 to 3.6 v i/o supply voltage ? C40oc to +85oc operating temperature range ? small package footprint ? 3 mm x 5 mm x 1 mm 24-pin lga package ordering information part number temperature range package description shipping FXLC95000CLr1 C40c to +85c lga-24 tape and reel 2 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
table of contents 1 typical applications ..............................................................4 2 software support ..................................................................4 3 related documentation.........................................................5 4 general description ..............................................................5 4.1 functional overview .....................................................5 4.1.1 rom content and usage ..................................7 4.2 pinout...........................................................................7 4.2.1 pin function description ....................................9 4.3 system connections.....................................................12 4.3.1 power supply considerations ........................... 12 4.3.2 general connections and layout recommendations............................................ 13 4.3.3 i2c reset considerations .................................. 14 4.3.4 FXLC95000CL as an intelligent slave .............. 14 4.3.5 FXLC95000CL as a sensor hub ...................... 16 4.4 sensing direction and output response ....................... 19 5 mechanical and electrical specifications .............................. 20 5.1 definitions .................................................................... 21 5.2 absolute maximum ratings .......................................... 21 5.3 operating conditions .................................................... 22 5.4 general dc characteristics .......................................... 23 5.5 supply current characteristics......................................23 5.6 accelerometer transducer mechanical characteristics 24 5.7 temperature sensor characteristics ............................ 25 5.8 adc characteristics ..................................................... 25 5.9 ac electrical characteristics.........................................26 5.10 general timing control..................................................27 5.11 interfaces ..................................................................... 28 5.12 flash parameters ......................................................... 31 6 package information ............................................................. 32 6.1 product identification markings....................................32 6.2 footprint and pattern information.................................32 6.3 tape and reel information ............................................ 35 6.4 package dimensions....................................................35 7 revision history .................................................................... 37 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 3 freescale semiconductor, inc.
1 typical applications this low-power intelligent sensor platform is optimized for a variety of applications. ? mobile phones/pmp/pda/digital cameras ? e-compass applications with tilt compensation ? smartbooks/e-readers/netbooks/laptops ? pedometers ? gaming and toys ? virtual-reality, 3d position feedback ? personal navigation devices (pnds) ? activity monitoring in medical and fitness applications ? security ? fleet monitoring and tracking ? power tools and small appliances 2 software support the xtrinsic intelligent sensing framework (isf) is a software framework built on top of freescales mqx real time operating system (rtos). isf offers an open programming model with library support for FXLC95000CL devices. the flexibility of this open programming model allows the FXLC95000CL to be delivered ready to accept a customers choice of firmware images. a number of pre-built firmware images are available for download from the freescale website, or, using codewarrior and isf, a customer may create their own custom firmware image incorporating sensor processing algorithms of their own design. sensor adapter libraries for a number of additional freescale sensors are also available for download enabling the FXLC95000CL to become a sensor hub. typical applications 4 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
3 related documentation the FXLC95000CL device's features and operations are described in a variety of reference manuals, user guides, and application notes. to find the most-current versions of these documents: 1. go to the freescale homepage at freescale.com. 2. in the keyword search box at the top of the page, enter the device number FXLC95000CL. 3. in the refine your result pane on the left, click on the documentation link. 4 general description 4.1 functional overview the FXLC95000CL platform consists of a three-axis, mems accelerometer and a mixed-signal asic with an integrated, 32-bit cpu. the mixed-signal asic can be utilized to measure and condition the outputs of the mems accelerometer, internal temperature sensor, or a differential analog signal from an external device. these measured values can be read at different sample rates through a subscription mechanism in the intelligent sensing framework (isf) and/or utilized internally by firmware for the FXLC95000CL device (freescale supplied or user-written). related documentation xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 5 freescale semiconductor, inc.
external clock domain internal clock domain analog front end sda1,scl1 8 bkgd/ms temperature sensor drive circuit c2v adc peripheral bus interface trim 3-axis accelerometer transducer system integration module interrupt controller 16 kb ram coldfire v1 16 kb rom 128 kb flash memory rgpio[15:0] flash controller i 2 c master spi master 2 x 8 port control 16-bit modulo timer programmable delay block two-channel tpm clock module ( 16 mhz) control and mailbox register set spi slave i 2 c slave 16 16 8 16 8 8 16 8 8 16 8 / / / sclk2. ssb2 mosi, miso, sp_scr[ps] ssb sclk miso mosi sda0 scl0 resetb int_i cpu / / pdb_a, pdb_b tpmch0, tpmch1 rgpio0, ... , rgpio15 figure 1. block diagram of the FXLC95000CL a block level view of the FXLC95000CL platform is shown in figure 1 and can be summaried at a high level as an analog/mixed mode subsystem associated with a digital engine. the analog sub-system is composed of: a 3-axis mems transducer an analog front end (afe) with: a capacitance-to-voltage converter an analog-to-digital converter a temperature sensor the digital sub-system is composed of: a 32-bit, coldfire v1 cpu with background debug module (bdm) memory: ram, rom, and flash rapid general purpose input/output (rgpio) port control logic timer functions: modulo timer module (mtim16) programmable delay timer (pdb) general-purpose timer/pulse-width modulation module (tpm) general description 6 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
? i 2 c master interface ? queued spi master interface (this interface has both send and receive fifos of size 16 bit wordlength and 4 words depth each. no dma.) ? i 2 c or spi slave interface ? system integration module (sim) ? clock-generation module the slave interfaces (either spi or i 2 c) operate independently of the coldfire cpu subsystem. this allows the host processor to access the slave interface at any time, including while the FXLC95000CL's cpu is in low-power, deep-sleep mode. host access can be set to trigger a FXLC95000CL cpu wakeup. 4.1.1 rom content and usage there are several classes of functions stored in rom: ? a boot program, including rom-based slave port command interpreter. ? a collection of utilities which can be invoked via the rom-based slave port command interpreter. ? rom functions which are callable from user code using the call_trap() function. for a detailed description of these items, refer to the FXLC95000CL hardware reference manual rom chapter. the FXLC95000CL device boots from a standard routine in rom. this boot function is responsible for a number of initialization steps (in particular the state of gpio8 pin is checked in order to select either i 2 c or spi interface as serial communication slave port), before transferring control if desired to user code in flash memory (when the boot from flash bit-field has been set). the rom contains a simple command interpreter capable of running a number of rom-based utility and test functions. these rom-based functions support flash memory programming and erasing, the protection of flash, the device reset, and the reading of device information. they also provide useful error codes. the FXLC95000CL platform is supplied with a fully erased flash memory. users can take advantage of the rom-based flash controller and slave port command-line interpreter to communicate with a virgin device and program custom firmware into the flash array. general description xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 7 freescale semiconductor, inc.
4.2 pinout rgpio14 / scl1 rgpio15 / sda1 v ssio v ddio v dd bkgd-ms / rgpio9 resetb rgpio11 / mosi1 rgpio10 / sclk1 rgpio7 / an1+ / tpmch1 rgpio6 / an0- / tpmch0 rgpio5 / pdb_a / int_o v ss rgpio4 / int_i v ssa rgpio8 / pdb_b v dda rgpio13 / ssb1 rgpio12 / miso1 scl0 / rgpio0 / sclk v ss sda0 / rgpio1 / mosi rgpio2 / scl1 / miso rgpio3 / sda1 / ssb figure 2. device pinout (top view) table 1. pin functions pin # default pin function 1 pin function #2 pin function #3 description 1 scl1 2 rgpio14 master i 2 c clock / rgpio14 2 sda1 3 rgpio15 master i 2 c data / rgpio15 3 v ssio i/o ground 4 v ddio i/o power supply 5 v dd digital power supply 6 bkgd/ms rgpio9 background debug - mode select / rgpio9 7 resetb 4 active low reset with internal, pullup resistor 8 scl0 rgpio0 sclk serial clock for slave i 2 c / rgpio0 / serial clock for slave spi 9 v ss digital ground 10 sda0 rgpio1 mosi serial data for slave i 2 c / rgpio1 / spi master output slave input 11 rgpio2 scl1 miso rgpio2 / serial clock for master i 2 c / spi master input slave output 12 rgpio3 sda1 ssb rgpio3 / serial data for master i 2 c / spi slave select 13 rgpio4 int_i rgpio4 / interrupt input 14 v ss must be connected to gnd externally 15 rgpio5 pdb_a int_o rgpio5 / pdb_a / interrupt output table continues on the next page... general description 8 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
table 1. pin functions (continued) pin # default pin function 1 pin function #2 pin function #3 description 16 rgpio6 an0- tpmch0 rgpio6 / adc input 0 / tpm channel 0 17 rgpio7 an1+ tpmch1 rgpio7 / adc input 1 / tpm channel 1 18 sclk1 rgpio10 master queued spi clock / rgpio10 19 mosi1 rgpio11 master queued spi master output slave input / rgpio11 20 miso1 rgpio12 master queued spi master input slave output / rgpio12 21 ssb1 rgpio13 master queued spi slave select / rgpio13 22 v dda analog power 23 5 rgpio8 pdb_b rgpio8 / pdb_b 24 v ssa analog ground 1. default pin function 1 represents the reset state of the device. pin functions may be changed via the sim pin mux- control registers. drive strength and pullup controls are programmed by the port control registers. 2. scl1 is available for use on pin (rgpio14) only when sim_pmcr1[a2] is not equal to "01". that setting would enable it for pin 11 (rgpio2). 3. sda1 is available for use on pin (rgpio15) only when sim_pmcr1[a3] is not equal to "01". that setting would enable it for pin 12 (rgpio3). 4. resetb defaults to input only, but can be configured as an open-drain, bidirectional pin. 5. gpio8/pdb_b = low at startup indicates that spi should be used as slave instead of the i 2 c module. 4.2.1 pin function description descriptions of the pin functions available on this device are provided in this section. sixteen of the device pins are multiplexed with rapid gpio (rgpio) functions. the default pin function column of table 1 lists which function is active when the device exits the reset state. user firmware can use the pin mux control registers in the system integration module (sim) to change pin assignments for these pins after reset. v ddio and v ssio i/o power and ground. v ddio ranges from 1.71v to 3.6v for this device. the device will not load the i 2 c bus if v ddio is not connected. parasitic paths to supply this power domain from other pins is not recommended. v dd and v ss digital power and ground. v dd is nominally 1.8v for this device. parasitic paths to supply this power domain from other pins is not recommended. v dda and v ssa general description xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 9 freescale semiconductor, inc.
analog power and ground. v dda is nominally 1.8v for this device. it is recommended that this supply voltage be filtered to remove any digital noise that may be present on the supply. resetb the resetb pin is an open-drain, bidirectional pin. at power up, it is configured strictly as an input pin. setting rcsr[dr] (reset control & status register drive reset bit) to one will cause the reset function to become bidirectional. using this feature, FXLC95000CL can reset external devices whenever it is reset for any purpose other than power-on-reset. slave i 2 c: sda0, scl0 slave i 2 c data and clock signals. FXLC95000CL may be controlled via this serial port or via the slave spi interface. at reset, sda0 and scl0 are open-drain, bidirectional in input mode, with the pullup resistor disabled. master i 2 c: sda1, scl1 master i 2 c data and clock signals. because the FXLC95000CL contains a 32-bit coldfire v1 cpu, it is fully capable of mastering other devices in the system via this serial port. state at reset: active. scl1 and sda1 are configured on pins 1 and 2, respectively. the alternate functionality on these pins is rgpio14 and rgpio15. analog-to-digital conversion: an0, an1 the on-chip adc can be used to perform a differential analog-to-digital conversion based upon the voltage present across pins an0(-) and an1(+). conversions for these pins are at the same sample data rate (sdr) as the mems transducer signals. state at reset: inactive. an[1:0] are secondary functions on rgpio[7:6], which own the pins at reset. rapid general purpose i/o: rgpio[15:0] the coldfire v1 cpu has a feature called rapid gpio or rgpio. this is a 16-bit input/output port with single-cycle write, set, clear, and toggle functions available to the cpu. the FXLC95000CL brings out all 16 bits of that port as pins of the device. state at reset: ? rgpio[15:14]: inactive. sda1 and scl1 own the pin at reset. general description 10 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
? rgpio[13:10, 8:2]: pin mux registers for these bits are configured as rgpio. pullups are disabled. rgpio functionality can be enabled via rgpio_enb[13:10, 8:2]. ? rgpio[9]: inactive. bkgd/ms owns the pin at reset ? rgpio[1:0]: inactive. sda0 and scl0 own the pin at reset. configuration details: ? rgpio[15:14] are configured as master i 2 c port at reset when rgpio_enb[15:14]=00 and pmcr[a3]=pmcr[a2]=00 or 10. they can only be configured as rgpio when pmcr[a3]=pmcr[a2]=01. rgpio_enb[15:14] must also be set to 11 for them to assume rgpio functionality. ? rgpio_enb[13:10] are used to configure rgpio[13:10]. ? pin function selections are made via the sim pin mux registers for rgpio[9:0]. interrupts: int_i this input pin may be used to wake the cpu from a deep-sleep mode. it can be programmed to trigger on either rising or falling edge or high or low level. this pin operates as a level 7 (high priority) interrupt. interrupts: int_o rgpio5 (pin 11) can be configured to function as an interrupt output pin. this interrupt can be asserted via software when a command response packet has been stored on the slave port mailboxes and is ready for the host to read. the host will see the interrupt and can read the data from the FXLC95000CL platform. the FXLC95000CL will automatically clear the interrupt once it recognizes that the response packet is being transmitted. this clearing action occurs while the packet is being read and prevents the host from falsely recognizing the same interrupt after the packet read is complete. state at reset: pin muxing is set to rgpio5 mode. debug/mode control: bkgd/ms at power-up, this pin operates as mode select. if low during power-up, the cpu will boot into debug halt mode. if high, the cpu will boot normally and run code. after power-on reset, this pin operates as a bidirectional, single-wire background debug port. codewarrior uses the background debug port to download code into on-chip ram and flash, and for debugging that code using breakpoints and single stepping. state at reset: mode select (ms). ms = 1'b0, at exit from reset boot to debug halt mode. general description xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 11 freescale semiconductor, inc.
ms = 1'b1, at exit from reset boot to run mode. state after reset: bkgd. the bkgd pin is a bidirectional, pseudo-open-drain pin used for communications with a debug environment. programmable delay block: pdb_a, pdb_b these are the two outputs of the programmable delay block (pdb). normally, the pdb is used to schedule internal events at some fixed interval(s) relative to start of either the analog or digital phase. by bringing the pdb outputs to these pins, it becomes possible for the FXLC95000CL to initiate some external event, also relative to start of analog or digital phase. for more information, refer to the FXLC95000CL hardware reference manual. timer: tpmch0 and tpmch1 these pins are the outputs for a general modulo 16 timer and general input/output capture (tpm) and pulse width modulation (pwm) functions. slave spi interface: sclk, mosi, miso, ssb slave spi clock, master-output slave-input, master-input slave-output, and slave-select signals. the FXLC95000CL may be controlled via this serial port or via the slave i 2 c interface. state at reset: in reset, these pins are configured according to i 2 c and rgpio[3:2] functions listed above. the pin may be reconfigured for spi use as part of the boot process. master spi interface: sclk1, mosi1, miso1, ssb1 master spi clock, master-output slave-input, master-input slave-output, and slave-select signals. state at reset: in reset, these pins are configured as rgpio[13:10] functions listed above. 4.3 system connections the FXLC95000CL platform offers the choice of connecting to a host processor through either an i 2 c or spi interface. it can also act as a master controller for i 2 c or spi peripherals and analog sensors. general description 12 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
4.3.1 power supply considerations ? an internal circuit powered by v dda provides the FXLC95000CL with a power- on-reset signal. for this signal to be properly recognized, it is important that v dd is powered up before or simultaneously with v dda . ? the voltage potential difference between v dd and v dda must not exceed 0.1 v. the simplest way to accomplish this is to power both pins from the same voltage source. ? when using the same voltage source, some digital noise might reach the analog section. to prevent this, connect a small inductor or ferrite bead in serial with both the v dda and v ssa traces. additionally, two ceramic capacitors (of approximately 1 f, and 100 nf, respectively) can be used to efficiently bypass the power and ground of both digital and analog supply rails. ? v ddio must rise up before or simultaneously with v dda /v dd . 4.3.2 general connections and layout recommendations ? provide a low-impedance path from the board power supply to each power pin (vdd, vdda, and vddio) on the device and from the board ground to each ground pin (vss, vssa, and vssio). ? the minimum bypass requirement is to place 0.01 C 0.1 f capacitors positioned as close as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the vdd/vss pairs, including vdda/ vssa. ceramic and tantalum capacitors tend to provide better tolerances. ? ensure that capacitor leads, associated printed circuit traces, and vias that connect to the chip vdd and vss (gnd) pins are as short as possible. ? bypass the power and ground. it is suggested that a high-frequency bypass capacitor be placed close to and on each power pin. bulk capacitance also is suggested, with it evenly distributed around the power and ground planes of the board. ? take special care to minimize noise levels on the vdda and vssa pins. an isolation circuit consisting of a ferrite bead and capacitors is suggested, to ensure that the voltage supplying the analog input is noise free. ? use separate power planes for vdd and vdda and separate ground planes for vss and vssa. connect the separate analog and digital power and ground planes as close as possible to power supply outputs. if both analog circuit and digital circuit are powered by the same power supply, it is advisable to connect a small inductor or ferrite bead in serial with both vdda and vssa traces. general description xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 13 freescale semiconductor, inc.
? it is highly desirable to physically separate analog components from noisy digital components by ground planes. do not place an analog trace in parallel with digital traces. it is also desirable to place an analog ground trace around an analog signal trace to isolate it from digital traces. ? if in-circuit debug capability is desired, provide an interface to the bkgd/ms pin. ? select resistors r2 and r3 in figure 3 to match requirements stated in the i 2 c standard. an example value of 4.7k is appropriate for the configuration shown. ? use the pcb footprint, solder mask, and solder stencil shown in footprint and pattern information. 4.3.3 i 2 c reset considerations if there is a reset during a slave i 2 c read transaction, then the slave device state machine will hang the bus, because it is waiting for the master clock. the host-driven reset signal provides an external way to reset the i 2 c state machine. 4.3.4 FXLC95000CL as an intelligent slave i 2 c pullup resistors, a ferrite bead, and a few bypass capacitors are all that are required to attach this device to a host platform. the basic configuration of the i 2 c interface is shown in figure 3. the voltage level on pin 23 (rgpio8) selects the slave-port format: i 2 c or spi. the rgpio pins can also be programmed to generate interrupts to the host platform, in response to the occurrence of application events. in this case, the pins should be routed to the external interrupt pins of the host processor. general description 14 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
fb 1 2 r3 4 .7 k? r2 4 .7 k? r6 1 k? i2c_clk i 2c_data int_out 1.8v v ddio c4 1 f c3 0.1 f c5 0.1 f c6 1 f 1 .8 v v ddio v ddio v ddio c1 1 f 1.8 v c2 0.1 f r1 notes: v dd = 1.8v pn = rgpion v dda = 1.8v (n from 0 to 15) v ddio = 1.71v to 3.6v quiet v dda for best performance. v ddio manual reset push button c 7 (optional emc filter ) pin 1 bdm header 10 k? u1 fxlc95000 1 3 6 4 5 2 7 8 9 1 0 1 1 1 2 13 14 15 16 2 4 2 3 2 2 2 1 2 0 19 17 18 rgpio14 / scl1 rgpio15 / sda1 v ssio bkgd / ms / rgpio9 v ddio v dd resetb rgpio11 / mosi1 rgpio10 / sclk1 rgpio7 / an1+ / tpmch1 rgpio6 / an0- / tpmch0 rgpio5 / pdb_a / int_o rgpio10 / int_i v ss scl0 / rgpio0 / sclk v ss sda0 / rgpio1 / mosi rgpio3 / sda1 / ssb rgpio2 / scl1 / miso v ssa rgpio8 / pdb_b v dda rgpio13 / ssb1 rgpio12 / miso1 v ddio r7 1 k? figure 3. FXLC95000CL as a slave (i 2 c interface) the basic configuration of the spi interface is shown in figure 4. the rgpio pins can also be programmed to generate interrupts to the host platform, in response to the occurrence of application events. in this case, the pins should be routed to the external interrupt pins of the host processor. general description xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 15 freescale semiconductor, inc.
r6 1 k? 1.8 v v ddio v ddio r 1 10 k? notes : v dd = 1.8v slave interface select v dda = 1.8v 1 = i 2 c v ddio = 1.7v to 3.6v 2 = spi quiet v dda for best performance . spi_clk spi_di ( mosi ) slave spi interface spi_ do ( miso ) spi_ en reset u1 fxlc95000 1 3 6 4 5 2 7 8 9 1 0 1 1 1 2 13 14 15 16 2 4 2 3 2 2 2 1 2 0 19 17 18 1.8v v ddio c4 1 f c3 0.1 f c5 0.1 f c6 1 f fb 1 2 c1 1 f 1.8 v c2 0.1 f rgpio14 / scl1 rgpio15 / sda1 v ssio bkgd / ms / rgpio9 v ddio v dd resetb rgpio11 / mosi1 rgpio10 / sclk1 rgpio7 / an1+ / tpmch1 rgpio6 / an0- / tpmch0 rgpio5 / pdb_a / int_o rgpio10 / int_i v ss scl0 / rgpio0 / sclk v ss sda0 / rgpio1 / mosi rgpio3 / sda1 / ssb rgpio2 / scl1 / miso v ssa rgpio8 / pdb_b v dda rgpio13 / ssb1 rgpio12 / miso1 v ddio r7 1 k? figure 4. FXLC95000CL as a slave (spi interface) 4.3.5 FXLC95000CL as a sensor hub the FXLC95000CL device includes a 32-bit coldfire v1 cpu associated with an ample amount of ram and flash memory, a master i 2 c and spi bus, and external differential analog inputs. these are the key hardware components that transform FXLC95000CL into an efficient and versatile sensor hub. the FXLC95000CL xtrinsic general description 16 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
intelligent sensing platform can interface and manage almost any type of sensor, digital or analog, such as pressure sensors, magnetometers, gyroscopes, and humidity sensors. the system supports external sensors interfacing to FXLC95000CL concurrently, via a combination of master spi and master i 2 c interfaces, and external differential analog inputs. besides FXLC95000CL rich connectivity, the 32-bit core and hardware multiply accumulator (mac) provide the processing power to collect, manipulate and fuse all sensors measurement locally and make appropriate decisions to optimize overall system power consumption. for example, FXLC95000CL can be programmed to operate effectively as a power controller for handheld units by enabling the host platform to put itself to sleep, with confidence that the FXLC95000CL will issue a wake-up request when an external event requires the host's attention. figure 5 shows the FXLC95000CL being used in this sensor hub configuration. note the simple connections. only a few bypass capacitors, a ferrite bead, and pullup resistors for the i 2 c buses are required. ? slave i 2 c interface is dedicated to communication with the host processor. interrupt output line int_o can be involved as well. ? master spi, master i 2 c, an0/an1 and interrupt input line int_i are available to interface a variety of external sensors general description xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 17 freescale semiconductor, inc.
notes : v dd = 1.8 v slave interface select v dda = 1.8 v 1 = i 2 c v ddio = 1.7 v to 3.6 v 2 = spi quiet v dda for best performance. 1 2 r3 4 .7 k? r2 4 .7 k? r6 1 k? u1 fxlc 95000 1 3 6 4 5 2 7 8 9 1 0 1 1 1 2 13 14 15 16 2 4 2 3 2 2 2 1 2 0 19 17 1.8 v v ddio c 4 1 f c3 0.1 f c5 0.1 f c6 1 f 1.8 v v ddio v ddio v ddio c1 1 f 18 c2 0.1 f r1 10 k? v ddio v ddio reset optional r 4 4.7 k? r5 4.7 k? optional optional optional slave i 2 c interface master spi interface master i 2 c interface alternate i 2 c interface on pins 1 and 2 1.8v fb rgpio 14/scl1 rgpio15/sda1 v ssio v ddio v dd bkgd/ms/ rgpio9 resetb s c l 0 / r g p i o 0 / s c l k v s s s d a 0 / r g p i o 1 / m o s i r g p i o 2 / s c l 1 / m i s o r g p i o 3 / s d a 1 / s s b v s s a r g p i o 8 / p d b _ b v d d a r g p i o 1 3 / s s b 1 r g p i o 1 2 / m i s o 1 rgpio11/mosi1 rgpio 10/sclk1 rgpio7/an 1+/tpmch1 rgpio6/an0-/tpmch0 rgpio5/pdb_a/int_o v ss rgpio 10/int_i i2 c_clk i 2c_data r7 1 k? v ddio figure 5. FXLC95000CL as a sensor hub (i 2 c interface) general description 18 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
notes : v dd = 1.8v slave interface select v dda = 1.8v 1 = i 2 c v ddio = 1.7v to 3.6v 2 = spi quiet v dda for best performance . 1 2 r6 1 k? u1 fxlc 95000 1 3 6 4 5 2 7 8 9 1 0 1 1 1 2 13 14 15 16 2 4 2 3 2 2 2 1 2 0 19 17 rgpio14/scl1 rgpio 15/sda1 v ssio v ddio v dd bkgd/ms/ rgpio9 resetb s c l 0 / r g p i o 0 / s c l k v s s s d a 0 / r g p i o 1 / m o s i r g p i o 2 / s c l 1 / m i s o r g p i o 3 / s d a 1 / s s b v s s a r g p i o 8 / p d b _ b v d d a r g p i o 1 3 / s s b 1 r g p i o 1 2 / m i s o 1 rgpio11/mosi1 rgpio10/sclk1 rgpio7/an1+/tpmch1 rgpio6/an0-/tpmch0 rgpio5/pdb_a/int _o v ss rgpio10/int _i spi_clk spi_di (mosi) 1 .8v v ddio c 4 1 f c3 0.1 f c5 0.1 f c6 1 f 1.8 v v ddio v ddio c1 1 f 18 1 .8v c2 0.1 f r1 10 k? v ddio r4 4. 7 k? r5 4.7 k? slave spi interface master spi interface master i 2 c interface alternate i 2 c interface on pins 1 and 2 analog input + analog input - spi_do (miso) spi_en int_out int_in fb spi_clk spi_do (mosi) spi_di (miso) spi_ss (slave select) r7 1 k? v ddio figure 6. FXLC95000CL as a sensor hub (spi interface) general description xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 19 freescale semiconductor, inc.
4.4 sensing direction and output response pin 1 top view side view landscape right xout @ 0g yout@ -1g zout @ 0g gravity landscape left xout @ 0g yout@ +1g zout @ 0g portrait up xout @ -1g yout@ 0g zout @ 0g portrait down xout @ +1g yout@ 0g zout @ 0g back xout @ 0g yout@ 0g zout @ -1g front xout @ 0g yout@ 0g zout @ +1g (top view) reference frame for acceleration measurement x y z figure 7. sensing direction and output response table 2. 1 g field-measured results g range full scale 1 1g 1 2 g 32,767 16,384 4 g 32,767 8192 8 g 32,767 4095 1. measured data in counts (16-bit word) after trimming. 5 mechanical and electrical specifications this section contains electrical specification tables and reference timing diagrams for the FXLC95000CL platform, including detailed information on power considerations, dc/ac electrical characteristics, and ac timing specifications. mechanical and electrical specifications 20 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
5.1 definitions cross-axis sensitivity the proportionality constant that relates a variation of accelerometer output to cross acceleration. this sensitivity varies with the direction of cross acceleration and is primarily due to misalignment. deep-sleep mode the devices lowest power state, when the system clock is stopped and the device performs no functions. in this mode, only a few exception events can wake the device. full range the maximum level of acceleration supported by the accelerometer's output signal, typically specified in g. for example, the output of an accelerometer program in 2 g mode will be linear when subjected to accelerations within 2 g. if the acceleration is larger than 2 g, the output will not be linear and may rail. hardware compensated sensor modules on this device include hardware correction factors for gain and offset errors which are calibrated during factory test using a least-squares fit of the raw sensor data. nonlinearity a measurement of deviation from perfect sensitivity. ideally, the relationship between input and output is linear and described by the sensitivity of the device. pin group device pins are clustered into a number of logical pin groupings in order to simplify and standardize electrical data sheet parameters. pin groups are defined in table 6. sensitivity describes the gain of the sensor and can be determined by applying a 1 g acceleration to it, such as the earth's gravitational field. the sensitivity of the sensor can be determined by subtracting the -1 g acceleration value from the +1 g acceleration value and dividing by two. software compensated in addition to the first-order hardware gain and offset calibration features, freescale implements advanced, nonlinear calibration functions to improve sensor performance. warm-up time the timefrom the initial application of powerfor a sensor to reach specified performance under specified operating conditions. zero-g offset describes the deviation of an actual output signal from the ideal output signal, if no acceleration is present. the expected ideal output signal, in this case, would be zero. a deviation from ideal value is called zero-g offset. offset is, to some extent, a result of stress on the mems sensor and, therefore, the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. 5.2 absolute maximum ratings absolute maximum ratings are stress ratings only and functional operation at the maximum ratings is not guaranteed. stress beyond the limits specified here may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. mechanical and electrical specifications xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 21 freescale semiconductor, inc.
this device contains circuitry protecting against damage due to high static voltage or electrical fields. however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ). table 3. absolute maximum ratings rating symbol condition minimum maximum unit digital supply voltage v dd C0.3 2.0 v analog supply voltage v dda C0.3 2.0 v i/o buffer supply voltage v ddio C0.1 4.0 v voltage difference v dd to v dda v dda C v dd C0.1 0.1 v voltage difference v ss to v ssa v ssa C v ss C0.1 0.1 v input voltage v in C0.3 v ddio + 0.3 v input/output pin clamp current i c C20 20 ma output voltage range v outod open-drain mode C0.3 v ddio + 0.3 v storage temperature t stg C40 +125 c mechanical shock sh 5k g drop test dr drop onto concrete slab 1.8 m table 4. esd and latch-up protection characteristics rating symbol min max unit human body model (hbm) v hbm 2000 v machine model (mm) v mm 200 v charge device model (cdm) v cdm 500 v latch-up current at t = 85 c i lu 100 ma caution this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. caution this is an esd sensitive device, improper handling can cause permanent damage to the part. mechanical and electrical specifications 22 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
5.3 operating conditions table 5. nominal operating conditions rating symbol min typ max unit digital supply voltage v dd 1.71 1.8 1.89 v analog supply voltage v dda 1.71 1.8 1.89 v i/o buffer supply voltage v ddio 1.71 3.3 3.6 v input voltage high v ih 0.7 * v ddio v ddio + 0.1 v input voltage low v il v ss C 0.3 0.3 * v ddio v operating temperature t a C40 25 85 c 5.4 general dc characteristics table 6. dc characteristics characteristic symbol condition(s) 1 min typ max unit output voltage high low drive strength high drive strength v oh pin groups 1 and 3 2, 3 iload = C2 ma iload = C3 ma v dd C 0.5 v output voltage low low drive strength high drive strength v ol pin groups 1 and 3 2, 3 iload = 2 ma iload = 3 ma 0.5 v total package output low current max total i ol for all pins i oht 24 ma total package output high current max total i oh for all pins i oht 24 ma hi-z (off state) leakage current |i oz | pin group 3 input resistors disabled 3 v in = v dd or v ss 0.1 1 a pullup resistor (pins resetb and bkgd/ms) r pu when enabled 17.5 52.5 k power-on-reset voltage v por 1.50 v power-on-reset hysteresis v por-hys 100 mv input pin capacitance c in 7 pf output pin capacitance c out 7 pf 1. all conditions at nominal supply: v dd = v dda = 1.8 v and v ddio = 3.3 v. 2. pin group 1 = resetb. 3. pin group 3 = rgpio[15:0]. mechanical and electrical specifications xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 23 freescale semiconductor, inc.
5.5 supply current characteristics table 7. supply current characteristics characteristic symbol condition(s) 1 min typ max unit supply current in stop nc mode 2 i dd-snc internal clocks disabled 2 a supply current in stop sc mode 3 i dd-ssc intenal clock in slow speed mode 15 a supply current in run mode 4 i dd-r internal clock in fast mode 5.4 ma 1. all conditions at nominal supply: v dd = v dda = 1.8 v and v ddio = 3.3 v. 2. stop nc : stop mode, no clock. 3. stop sc : stop mode, slow clock. 4. run: normal fast mode. total current with the analog section active, 16 bits adc resolution selected, mac unit used, and all peripheral clocks enabled. 5.6 accelerometer transducer mechanical characteristics table 8. accelerometer characteristics characteristic symbol condition(s) 1 min typ max unit full range a fr 2 g 2 g 4 g 4 8 g 8 sensitivity/resolution (16 bits adc resolution) (after trimming) a sens 2 g 0.061 mg/lsb 4 g 0.122 8 g 0.244 zero-g level offset accuracy (pre-board mount) off pbm 2 g C100 +100 mg 4 g 8 g nonlinearity best fit straight line a nl 2 g 0.25 % a fr 4 g 0.5 8 g 1 sensitivity change versus temperature tc sa 2 g 0.17 %/c zero-g level change versus temperature 2 tc off 0.2 mg/c zero-g level offset accuracy (post-board mount) off bm 2 g C100 +100 mg 4 g 8 g output data bandwidth bw odr/2 3 hz noise density noise 2g, odr=488hz, 4xoversampling 4 100 g/sqrt(hz) 3.12 mg (rms) table continues on the next page... mechanical and electrical specifications 24 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
table 8. accelerometer characteristics (continued) characteristic symbol condition(s) 1 min typ max unit 8g, odr=488hz, 4xoversampling 4 120 g/sqrt(hz) 3.75 mg (rms) cross-axis sensitivity C5 5 % 1. all conditions at nominal supply: v dd = v dda = 1.8v and v ddio = 3.3v. 2. relative to 25c. 3. odr: output data rate or the sampled data rate of the system. 4. performance specification is with cpu being inactive during sensor data acquisition 5.7 temperature sensor characteristics table 9. temperature sensor characteristics characteristic symbol condition(s) 1 min typ max unit full scale range t fsr C40 +85 c sensitivity tsens 16 bit data word 0.0025 c/lsb non-linearity t nl 2.4 % fsr 1. all conditions at nominal supply: v dd = v dda = 1.8 v and v ddio = 3.3 v. 5.8 adc characteristics table 10. adc characteristics characteristic symbol condition(s) 1 min typ max unit external input voltage v ai voltage at an0 or an1 0.2 1.1 v external differential input voltage 2 v adi an1 C an0 C0.9 0.9 v full-scale range v fs 1.8 v programmable resolution r es 10 14 16 bits conversion time @ 14 bits resolution (three-sample frame, xyz) t c 207 s integral nonlinearity inl full scale 15 lsb differential nonlinearity dnl 2 lsb input leakage i ia 2 a total capacitance c in 7 pf series resistance r in 6 k 1. all conditions at nominal supply: v dd = v dda = 1.8 v, v ddio = 3.3 v, and r es = 14 unless otherwise noted. 2. the external adc input pins go through a buffer line that is powered by v ddio . noise on the v ddio line degrades the external adc signal. mechanical and electrical specifications xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 25 freescale semiconductor, inc.
5.8.1 adc sample rates the system clock is 16 mhz with the first sample rate generated by dividing the system clock by 4096 (16 mhz / 4096 = 3906.25 hz). subsequent sample rates are all a sequence of divide-by-two. the FXLC95000CL platform's internal frame timer supports the following sample rates (frames per second (fps)): 3906.25 fps 1953.13 fps 976.56 fps 488.28 fps 244.14 fps 122.07 fps 61.04 fps 30.52 fps 15.26 fps 7.63 fps 3.81 fps 1.91 fps 0.95 fps 0.48 fps 0.24 fps notes ? at the fastest sampling rate of 3906.25 hz, there is not enough time to complete the adc conversions highest- bit resolution, so only 10-,12-,and 14-bit resolutions are available at that rate. all of the adc resolutions (10-,12-, 14-, and 16-bit) are available at all other sample rates. ? freescale's intelligent sensor framework (isf) uses the software-triggered sample mode, using the mtim16 timer to set the sample period. this allows the specification of sample periods to microsecond resolution. mechanical and electrical specifications 26 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
5.9 ac electrical characteristics tests are conducted using the input levels specified in table 5. unless otherwise specified, propagation delays are measured from one 50% point to the next 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in figure 8. figure 8. input signal measurement references figure 9 shows the definitions of the following signal states: ? data active state, when a bus or signal is driven, and enters a low impedance state ? data tri-stated, when a bus or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh figure 9. signal states 5.10 general timing control table 11. general timing characteristics characteristic symbol condition(s) 1 min typ max unit v dd rise time t rvdd 10% to 90% 1 ms por release delay 2 t por power-up 0.35 1.5 ms table continues on the next page... mechanical and electrical specifications xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 27 freescale semiconductor, inc.
table 11. general timing characteristics (continued) characteristic symbol condition(s) 1 min typ max unit warm-up time t wu from stop with no clock 7 sample periods frequency of operation f oph full-speed clock 16 mhz f opl slow-speed clock 62.5 khz system clock period t cych full-speed clock 62.5 ns t cycl slow-speed clock 16 s full/slow clock ratio 256 oscillator frequency absolute accuracy @ 25c full-speed clock C5 +5 % oscillator frequency variation over temperature (C40c to 85c vs. ambient) slow-speed clock C6 +6 % minimum reset assertion duration t ra 4t 3 1. all conditions at nominal supply: v dd = v dda = 1.8 v and v ddio = 3.3 v. 2. time measured from v dd = v por until the internal reset signal is released. 3. t = period of one system clock cycle. in full-speed mode, t is nominally 62.5 ns. in slow-speed mode, t is nominally 16 s. 5.11 interfaces the FXLC95000CL may be controlled via its included slave i 2 c module that can be active 100% of the time. the fxlc95000 also includes a master i 2 c that should be used only when the system clock is running at full speed. the master interface is intended to be used to communicate with other, external sensors. figure 10. i 2 c standard and fast-mode timing mechanical and electrical specifications 28 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
5.11.1 slave i 2 c table 12. i 2 c speed ranges mode max baud rate (f scl ) minimum bit time minimum scl low (t low ) minimum scl high (t high ) min data set- up time (t su; dat ) min/max data hold time (t hd; dat ) standard 100 khz 10 s 4.7 s 4 s 250 ns 0 s/3.45 s 1 fast 400 khz 2.5 s 1.3 s 0.6 s 100 ns 0 s/0.9 s 1 fast + 1 mhz 1 s 500 ns 260 ns 50 ns 0 s/0.45 s 1 high-speed supported 2.0 mhz 0.5 s 200 ns 200 ns 10 ns 0 ns/70 ns (100 pf) 2 1. the maximum t hd;dat must be at least a transmission time less than t vd;dat or t vd;ack . for details, see the i 2 c standard. 2. timing met with ife = 0, ds = 1, and se = 1. for more information, refer to port control registers in the FXLC95000CL hardware reference manual. 5.11.2 master i 2 c timing the master i 2 c should only be used when the system clock is running at full speed. do not attempt to use the master i 2 c across frames in which a portion of the time is spent in low-speed mode. table 13. master i 2 c timing characteristic symbol standard mode fast mode unit min max min max scl clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd; sta 4.0 0.6 s low period of the scl clock t low 4.7 1.3 s high period of the scl clock t high 4.0 0.6 s set-up time for a repeated start condition t su; sta 4.7 0.6 s data hold time for i 2 c bus devices t hd; dat 0 1 3.45 2 0 1 0.9 2 s data set-up time t su; dat 250 100 3, 4 ns set-up time for stop condition t su; sto 4.0 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 s 1. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, a negative hold time can result, depending on the edge rates of the sda and scl lines. 2. the maximum t hd; dat must be met only if the device does not stretch the low period (t low ) of the scl signal. mechanical and electrical specifications xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 29 freescale semiconductor, inc.
3. set-up time in slave-transmitter mode is 1 system-clock period (16 mhz = 62.5 ns). there is no fifo on the i 2 c. 4. a fast-mode, i 2 c bus device can be used in a standard mode i 2 c bus system, but the requirement t su; dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. according to the standard mode, i 2 c bus specification, if such a device stretches the low period of the scl signal, it must output the next data bit to the sda line trmax + t su ; dat = 1000 + 250 = 1250 ns before the scl line is released. 5.11.3 spi interfaces (slave and master) figure 11 and table 14 describe the timing requirements for the spi system. 1 12 11 3 2 4 4 7 9 10 8 10 6 5 ss (input) sclk (input) mosi (input) miso (output) note: not definednormally the msb of the character just received. slave msb out bit 6...1 slave lsb out not defined (see note) lsb in msb in bit 6...1 figure 11. slave and master spi timing table 14. slave and master spi timing drawing number function symbol min max unit operating frequency f op 0 f oph /4 hz 1 sclk period t sclk 4 t cych 2 enable lead time t lead 0.5 t cych 3 enable lag time t lag 0.5 t cych 4 clock (sclk) high or low time t wsclk 200 ns table continues on the next page... mechanical and electrical specifications 30 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
table 14. slave and master spi timing (continued) drawing number function symbol min max unit 5 data set-up time (inputs) t su 15 ns 6 data hold time (inputs) t hi 25 ns 7 access time t a 25 ns 8 miso disable time t dis 25 ns 9 data valid (after sclk edge) t v 25 ns 10 data hold time (outputs) t ho 0 ns 11 rise time input t ri 25 ns output t ro 25 ns 12 fall time input t fi 25 ns output t fo 25 ns 5.12 flash parameters the FXLC95000CL platform has 128 kb of internal flash memory. there are rom functions that allow the erasing and programming of the flash memory. a chip supply voltage of 1.8 v is sufficient for the flash programming voltage. the smallest block of memory that can be written is four bytes and those four bytes must be aligned on a four byte boundary. the largest block of memory that can be programmed is 256 bytes and the block must start at a 256-byte boundary. flash programming blocks must start on a 4-byte boundary and cannot cross a 256- byte page boundary. table 15. flash parameters parameter value word depth 32,768 row size 256 bytes page erase size (erase block size) 4 rows = 1024 bytes maximum page programming size 1 row = 256 bytes minimum word programming size 4 bytes memory organization 32,768 32 bits = 128 kb total endurance 20,000 cycles minimum data retention > 100 years at room temperature mechanical and electrical specifications xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 31 freescale semiconductor, inc.
6 package information the FXLC95000CL is contained in a 24 pin, 3 mm by 5 mm by 1 mm lga package. 6.1 product identification markings top view 263 fxlc950 sbwgvw trace code wafer lot date code assembly split lot part number freescale code package information 32 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
6.2 footprint and pattern information notes: 1. all measurements are in millimeters. 2 . there is a 0.015 mm shrink on each direction from copper footprint. 2.225 6 7 89 10 1112 13 14 15 1 2 3 5 16 17 18 19 20 21 23 24 + + + + + 0.350 0.250 0.100 0.100 0.250 0.500 0.375 package footprint 0.500 + 22 1.225 + 4 pcb copper pattern 0.650 0.250 0.250 + + + + + + 1.375 2.375 pcb solder-mask pattern 0.850 3.450 0.850 0.225 2.450 + + 1.375 + 2.375 + + pcb stencil pattern (2) 0.220 0.620 + + 2.375 + + 1.375 package information xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 33 freescale semiconductor, inc.
overlay drawing 3.000 5.600 + + + + + + + + + + + + + + + + + + + 5.000 3.600 + + + + + 0.015 zoom-in drawing + + + + + + + + + + + 0.200 0.100 0.225 0.250 0.100 note: all measurements are in millimeters. package information 34 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
6.3 tape and reel information 6.3.1 tape dimensions notes: 1. measured from center line of sprocket hole to center line of pocket. 2 . cumulative tolerance of 10 sprocket holes is + 0.20. 3. other material available. 4. all dimensions in millimeters , unless otherwise stated. ( 1) ( 2) (1) 6.3.2 device orientation pin 1 location reel sprocket hole package information xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 35 freescale semiconductor, inc.
6.4 package dimensions case 2208-01, issue o, 24-lead lga package information 36 xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. freescale semiconductor, inc.
7 revision history revision number revision date description 1.0 may 2013 initial public release 1.1 august 2013 ? changed zero-g level change versus temperature (tc off ) specification in table 8 ? added rms noise specification for 2 g and 8 g in table 8 ? removed footnote in table 9 ? restated non-linearity in different units (% fsr) in table 9 1.2 august 2013 ? changed zero-g level change versus temperature (tc off ) specification in table 8. ? changed sensitivity tsens specification in table 9. revision history xtrinsic FXLC95000CL intelligent, motion-sensing platform, rev1.2, 8/2013. 37 freescale semiconductor, inc.
how to reach us: home page: freescale.com web support: freescale.com/support information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. freescale, the freescale logo, codewarrior, coldfire, and energy efficient solutions logo are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. xtrinsic is a trademark of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012C2013 freescale semiconductor, inc. document number FXLC95000CL revision 1.2, 8/2013

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